Contents 📚
- Basic Concepts: Description of VHDL and its significance in digital circuit design.
- Digital Logic Fundamentals: Basic principles of digital electronics and their application in circuit design.
- Concurrent and Sequential Statements: Organizing VHDL statements to create efficient circuits.
- Structural Design: Composing complex circuits using simpler components with VHDL.
- Selected and Conditional Signals: Implementing conditional logic in VHDL designs.
- Components and Generation: Creating reusable components and generating efficient design structures.
- State Diagrams: Designing and representing digital system behaviors using state diagrams.
- Simulation and Verification: Using software tools to simulate and verify VHDL designs, especially in the context of the Basys 3 board and Vivado.
Basys 3 Development Board Components and Features 🛠️
- Clock: An internal clock that Verilog projects can utilize, featuring an additional line for configuration.
- Switches: 16 switches located along the bottom edge of the board.
- LEDs: 16 small LEDs positioned above the switches along the bottom of the board.
- 7-Segment Display: A 4-digit 7-segment display.
- Pushbuttons/Buttons: Five accessible buttons in the middle of the board. These buttons are designed to prevent bouncing.
- PMOD Headers: These are 4-pin and 12-pin connectors located on the sides of the board, allowing communication with external devices.
- VGA Connector: VGA port for graphical display capabilities.
- USB Connections: Interfaces for communication through USB.
- Quad SPI Flash: Flash memory for storage.
Vivado Usage 💻
Generate .Bin File 📔
Click generate bitstream (can be carried out step by step, Run Synthesis - Run Implementation - Generate bitstream) and generate bit files and bin files.
Program Basys3 ⚙️
Step-by-step instructions for programming the Basys 3 board with Vivado.
Resources 👨🏻🔬
Projects 🚀
- Basys3MusicNotes: Implementation of a musical system on a Basys 3 board.
- BlinkyLed: Basic example of a blinking LED on an FPGA.
- Constraints Template: Template for FPGA project constraints.
- Dec3_8: Design of a 3-to-8 decoder in VHDL.
- Digital-Chronometer: Digital chronometer implemented on an FPGA.
- Modules Template: Template for reusable VHDL modules.
- Random-Generator: Random number generator using digital logic.